Current computing power anxiety is not evenly distributed but exhibits significant structural differentiation.
High-end training compute in the cloud remains tight, with advanced process nodes, HBM, and packaging capacity jointly constraining delivery. Meanwhile, although edge AI has gained considerable attention, stable, scalable, and profitable business loops remain scarce. More precisely, the industry is transitioning from "who can build a Demo" to a phase of differentiation where "who can achieve mass production and sustained profitability" becomes the key criterion.
In this environment, where capital has become rational and even somewhat stringent, Hangzhou Weilu Intelligent Technology Co., Ltd. (abbreviated as VELOXIS AI) was established in Qiantang District, Hangzhou, in July 2026. It completed an angel round of several tens of millions CNY in September (led by Guoxin Zhongshu Tongling Science and Technology Innovation Fund), followed by an Angel+ round in October, securing two rounds of financing within three months of its inception.
VELOXIS AI has chosen the GPNPU (General-Purpose Programmable Neural Processing Unit) technical path. Sitting between NPU (Neural Processing Unit) and GPU (Graphics Processing Unit), is this approach a chimera, or the optimal solution for large model inference at the edge?
Over the past few years, the edge AI chip market has undergone fierce reshuffling. We have seen many projects fail, most trapped in an "impossible triangle": under limited Power and Area constraints, it is difficult to simultaneously achieve high Performance and high Flexibility.
Traditional NPU solutions, by hardcoding operator circuits, indeed maximize energy efficiency. However, in the era of large models, the rapid iteration of Transformer architectures and their variants turns the "specialization" of NPUs into a "limitation." Adapting to new operators often requires lengthy firmware upgrades or even renders the chip obsolete.
Conversely, while general-purpose GPUs offer unparalleled flexibility, their massive control logic and cache systems make them ill-suited for space-constrained edge devices. For scenarios highly sensitive to power consumption, such as robotics and edge boxes, the high energy consumption of GPUs is often unbearable.
The GPNPU path chosen by VELOXIS AI essentially attempts to break this triangle. Based on publicly disclosed information, its core architecture aims to fuse the high energy efficiency of NPUs with the programmability of general-purpose processors. This is not merely physical stacking but deep integration at the instruction set and microarchitecture levels.
For downstream customers, the greatest appeal of this architecture lies in "compatibility for upgrading existing systems." In industrial control and smart manufacturing scenarios, customers do not need to overhaul their existing ARM or x86 main control architectures; they can simply introduce GPNPUs via acceleration cards or modules to gain the capability to run large models locally. This smooth upgrade path—"changing the engine without replacing the heart"—holds immense disruptive potential in a market environment that currently places extreme emphasis on ROI (Return on Investment).
"Third-rate chip companies make hardware, second-rate chip companies make drivers, and first-rate chip companies make ecosystems." The entry point to the ecosystem is the compiler.
In this funding round, VELOXIS AI explicitly stated that funds will be primarily invested in the productization of the TileFlow compiler and software stack.
In heterogeneous computing, hardware performance is often just paper value; the true bottleneck lies in the usability of the software stack. Developers facing various proprietary SDKs and obscure operator libraries are often deterred. If a chip cannot allow developers to invoke resources "transparently" like CUDA, no matter how powerful its compute, it remains just data in a laboratory.
The emergence of TileFlow is clearly aimed at solving this problem. Although detailed underlying technical specifications of this compiler are currently limited in public disclosures, its positioning points towards compilation paths involving "high-level computation graph description to automatic mapping of low-level hardware primitives," aiming to lower barriers for model migration and deployment. Regarding whether it uses specific intermediate representations or compilation frameworks as its implementation basis, public information is insufficient for judgment, so no excessive speculation is made here. What can be confirmed is its public compatibility with mainstream inference frameworks such as llama.cpp and vLLM, which itself indicates that its toolchain orientation is to "integrate with the ecosystem" rather than "start from scratch."
Elevating the compiler to a strategic height equal to that of the chip architecture demonstrates that VELOXIS AI's team understands clearly: the success of GPNPU depends half on architecture and half on the toolchain. Only when developers can migrate PyTorch or TensorFlow models at low cost can the "generality" value of GPNPU be truly realized. This is also the soft barrier most valued by investors in this funding round.
Another keyword mentioned in the financing information is "VLX-64" and "first-generation chip tape-out."
From public information, VLX-64 is positioned as the first product (in acceleration card form), and the use of Angel+ round funds includes expressions such as "first-generation chip tape-out and engineering verification." As for whether the chip is currently in MPW tape-out, engineering verification, or mass production preparation stages, public disclosures are insufficient, and excessive interpretation should be avoided. What can be confirmed is that the company is advancing the tape-out and verification work for its first-generation chip while simultaneously initiating the construction of its delivery system—a pace that already reflects the compactness of its R&D progress. As its first verification chip, VLX-64 carries the heavy responsibility of validating the feasibility of the GPNPU architecture. Our focus is not only on its peak compute but also on its actual inference frame rate and energy efficiency ratio when running mainstream large models (such as Llama 3, Qwen, etc.).
Additionally, the fund usage mentions "IP customer delivery system construction," which implies that VELOXIS AI may adopt a dual-wheel drive model of "chip + IP licensing." For leading terminal manufacturers, purchasing IP for SoC integration is often more attractive than buying standalone chips. This flexible commercial strategy undoubtedly broadens its market survival space.
VELOXIS AI's founding team originates from EPFL (École Polytechnique Fédérale de Lausanne) and UCSD, with a background in joint R&D with TSMC (Taiwan Semiconductor Manufacturing Company). This combination of "academic theoretical depth" and "industrial practical experience" forms the basis for attracting industrial capital such as Guoxin Zhongshu.
The GPNPU path theoretically aligns perfectly with the needs of edge large models, but in engineering implementation, balancing the area overhead brought by programmability and ensuring that the TileFlow compiler truly "understands" developer intent will be the hurdles VELOXIS AI must cross next.
This article is written based on publicly disclosed financing information and related technical materials. Company names, technical terms, and data mentioned herein are for reference only, intended to promote industry technical exchange and discussion, and do not represent absolute endorsement of any technical path.
Editor: Shuo Xin Yu - Xiaomingba